Two milestones before a memory-first inference chip earns 2027 capacity

Your capacity plan needs a yes/no answer on a memory-first accelerator before the budget lock. The trade-off is reserving capacity before Asimov's scheduled production. Positron's simulations show a rack using its silicon can deliver up to 26 times the tokens per dollar of Nvidia's Blackwell GB300 NVL72 appliance.

Confirm tapeout before you reserve capacity

Positron AI announced an $875 million Series C financing at a $5 billion post-money valuation on September 10, 2026. Positron said the new capital will pay for Asimov tapeout and the Titan production ramp, following a 50-plus-rack Atlas deployment at Oracle Cloud Infrastructure in Reno, Nevada. The gate is physical silicon out of the foundry, then a paying production workload.

Asimov is scheduled for TSMC N3P tapeout at year-end 2026, with H2 2027 production and 288 GB to 2,304 GB of memory attached to each chip. If the tapeout slips, the capacity plan needs a named fallback rack, with a power and network budget, before the vendor date is treated as a commitment. If the tapeout moves, the plan can shift without re-opening the budget. A paying production workload tests the same cost case under real context lengths, real batch sizes, real failure rates, and sustained decode. It shows whether the memory subsystem stays warm under production load, not just a burst.

Build the test around decode, not prefill. Decode is where memory bandwidth usually binds, and where a memory-first design should show its edge. Pick a long-context workload, fix the batch size, and measure tokens per second per dollar on your current rack. Then ask the vendor to run the same workload on a reference system. If the answer is only a number, the gate fails.

Run the bandwidth math before you sign

Positron claimed that its next-generation systems can use over 90 percent of the memory bandwidth available to them, and that commodity LPDDR5X lets them avoid tight HBM and CoWoS supply chains. It also claimed that typical AI accelerators use under 30 percent of HBM module bandwidth, whereas its appliances can access over 90 percent of LPDDR5X throughput.

Asimov's per-chip memory capacity ranges from 277 gigabytes to 2.3 terabytes, and its chips can be linked into clusters of up to 16,384 chips. That range changes long-context decode math: more memory per chip means fewer offloads to slower storage. If a workload needs the top of the range, the top config clears it without an extra memory tier.

Keep the cost test tied to your own unit economics. A token changes value when context length, cache hit rate, and concurrency change. If the vendor's number uses a short prompt and a large batch, it may not survive your production mix. Ask for the context length, the batch size, and the price per rack-hour. If those fields are missing, the number is not a capacity input. Use the same measurement period. Keep the output as a number your finance team can audit. Record the context length, batch size, and rack-hour price in the same row as the token count, so the audit trail is one table.

Keep the checklist to gates and a cost test

Use the list below when a memory-first accelerator enters a capacity plan. Each item is a yes/no check you can run in a minute. Keep it in the capacity review, not in a vendor deck. Use it before the budget lock. The final test is realized memory-bandwidth utilization against long-context decode cost per token.

• Confirm Asimov tapeout on TSMC N3P at year-end 2026.
• Confirm a paying production workload.
• Check that the vendor reports realized memory-bandwidth utilization above 90 percent.
• Check that the cost-per-token claim is tied to a named workload, not a simulation.

Run the cost test before you sign, and run it again after production starts.